The present invention relates to a semiconductor device, and in particular, it relates to a semiconductor device which has a plurality of power semiconductor elements such as insulated gate bipolar transistors (IGBT) arrayed and integrated into a module.
Recently, the high-speed switching pulse width modulation control (PWM) method has become a mainstream in the electric power control equipment for controlling electric power supply. As its control elements, bipolar transistors, field effect transistors (FET), IGBT are utilized. Among them, IGBT devices have been widely applied for their excellent efficiencies from industrial applications such as elevators, trains, machine tools, uninterruptible power supplies to home appliances such as air-conditioners, electric ovens, and so on.
These electric power control devices which are increasingly required to control higher voltages and currents to comply with a need for faster operation and greater output tend to increase heat generation in their semiconductor devices. Thereby, it has become most important for them to be able to dissipate the heat generated in the semiconductor devices. As the structure of their semiconductor devices, there is known such a structure in which an insulation plate, a metal heat dissipation plate, a thermal stress relieving material and a semiconductor device are bonded sequentially using a brazing material such as solder or the like on a metal support plate. The thermal stress relieving material is utilized to prevent the semiconductor device from cracking due to a thermal stress resulting from a difference between a thermal expansion coefficient of approximately 4.5.times.10.sup.-6 /.degree. C. for Si which constitutes the semiconductor device and a thermal expansion coefficient of approximately 17.times.10.sup.-6 /.degree. C. for Cu which constitutes the metal heat dissipation plate. Since the heat dissipation plate must have a large thermal conductivity to ensure an improved heat dissipation and a good electric conductivity for serving as an electrode for the semiconductor device as well, Cu is generally used for it. The insulation plate is necessary for electrically insulating from the metal support plate. Al.sub.2 O.sub.3 ceramics is most widely utilized as its substrate because of its excellent electric properties in withstand voltage and resistivity, and of its mechanical strength and manufacturing cost as well. For the metal support plate since it contributes much to the heat dissipation thereby it must have a greater thermal conductivity, Cu is preferably utilized. Any electric power supply control equipment having the above-mentioned construction undergoes repetition of exothermic and cooling cycles while repeating start and stop of operation. Thereby, a thermal stress due to a difference between thermal expansion coefficients is exerted on the brazing materials which bond the metal dissipation plate, the metal support plate and the insulation plate so as to cause a crack or a gap to occur therebetween. In order to solve such problems associated with the prior art, the Japanese Patent Application Laid-Open No.5-136286 discloses as shown in FIG. 4 that the mesh member 18 having the thermal expansion coefficient which is adapted to be intermediate between those of the heat dissipation plate 3 and the insulation plate 2 is inserted therebetween to reinforce the soldering layer by forming a uniform thickness soldering layer, thereby to prevent the occurrence of cracks and gaps due to the thermal stress as described above. Further, the Japanese Patent Application Laid-Open No.4-287952 discloses as shown in FIG. 5 that the thermal stress relieving materials 20, 23 including Mo or the like are provided in the bonding portion between the insulation plate and the metal dissipation plate to prevent the occurrence of the cracks and gaps due to the aforementioned thermal stresses.
Further, the Japanese Patent Application Laid-Open No.61-237456 discloses that each linear expansion coefficient and each longitudinal elasticity coefficient of each structural member to be utilized in the module are specified to minimize the stress. On the other hand, as some optimization methods for optimizing the thickness of each plate member to be utilized in the module, there is known such one as disclosed, for example, in the Japanese Patent Application Laid-Open No.59-46036 in which the thickness of the insulation plate used in the module is defined to be 0.15-0.35 mm to improve the heat dissipation capability and the heat cycle resistance of the module. Further, the Japanese Patent Application Laid-Open No.60-257141 discloses that the insulation plate, the terminal plate, the stress relieving plate and the semiconductor chip are mounted on the metal base sequentially in lamination by means of soldering wherein the thickness of the stress relieving plate is adapted to become thicker than that of the terminal plate to reduce the stress exerting on the soldering. The Japanese Patent Application Laid-Open No.60-1837 discloses that the metal support on which the semiconductor chip is to be soldered is provided with protrusions which serves to define a thickness of the solder filler material and prevent the transversal shifting of the semiconductor chip so as to provide precision soldering in thickness and position.
In the foregoing method for reinforcing the solder layer by providing the uniform thickness soldering layer by inserting the metal mesh member, although many of the above-mentioned problems has been solved, there still remains crucial problems to be solved since the occurrence of cracks has been recognized when they are applied in practice, thus this method has provided only a partial solution but not an adequate solution. Further, the method which uses a thermal stress relieving member such as Mo or the like in the bonding portion between the insulation plate and the metal heat dissipation plate is associated with such problems that the manufacturing cost increases due to an increased number of bonded members and that the defect occurrence ratio increases with the increased number of bonded members, thereby, failing actually to solve the problems.
Further, even arranging such that the linear expansion coefficients and longitudinal elasticity coefficients of respective members used inside the module are specified to minimize the stresses exerting on the solders, since in an actual module the dimensions of plates being laminated from the semiconductor chip toward its supporting substrate are caused to change, the plate members which apply stresses on the soldering layers differ from between portions at their locations immediately below the semiconductor chip and to the other locations. Further, since the stresses applied on the soldering fillers become a maximum in the peripheral portion, and from which a crack in the solder initiates and propagates, it becomes important to balance the stress immediately below the chip and the stress in the peripheral portion.
Therefore, it is necessary to examine an optimum thickness for each component of the structure depending on its lamination structure. However, in the foregoing prior art, the plate thickness of each layer construction is specified identical on the same plane, thus, there has been no attempt to optimize individual lamination structures.
In the Japanese Patent Application Laid-Open No.59-46036, however, there has been discussed partially on the warp which occurs in the bonded members due to a difference in their thermal expansion coefficients, and there has been employed a method for reducing the stress exerting on the soldering layer as well as lowering the warp amount in the bonded lamination members.
However, this prior art has not taken into account such cases where bonding process is repeated plural times, and a warp formed in a composite material which was bonded precedently will alter the behavior thereof in a subsequent bonding process thereby decreasing the bonding strength of the solder.